Issue in Multi Excerpt Plugin: missing <p> tag at start of content

Description

There is an issue with Atlassian macro ‘Excerpt’. Html export is showing missing html tag of content inside Excerpt macro.

Example: (Storage format of a page using Excerpt macro)
<ac:structured-macro ac:name="excerpt"><acarameter ac:name="atlassian-macro-output-type">INLINE</acarameter><ac:rich-text-body>
<p>In UVM-ML OA, data is passed between components using TLM ports or UVM configuration. The process of passing items requires:</p>
<ul>
<li>Knowing which type on the target side matches the type in the initiating language. This is referred to as type mapping.</li>
<li>The serialization and de-serialization needs to match in order to get the correct data on the receiving side.</li></ul>
<p>For&nbsp;<em><strong>e</strong></em>&nbsp;structs, the default is that physical fields (marked with&nbsp;<strong>%</strong>) are packed/unpacked.</p>
<p>For SystemVerilog items, the default is serialization of the fields that were added with the&nbsp;<strong>uvm_field_</strong>* macro.&nbsp;</p>
<p>For passing items between components, you should:</p>
<ul>
<li>Implement the data items:
<ul>
<li>Make sure both ports, in both languages, handle same data items.&nbsp;
<ul>
<li>If the items differ:
<ul>
<li>Implement a new type, in either language.</li>
<li>You might have to implement a converter, converting from the original data item handled by the UVC, to the new data item</li></ul></li></ul></li></ul></li>
<li>Instantiate and connect the required ports<span>&nbsp;</span></li></ul>

Html export output of same content is:

<div id="main-content" class="wiki-content group">
In UVM-ML OA, data is passed between components using TLM ports or UVM configuration. The process of passing items requires:</p><ul><li>Knowing which type on the target side matches the type in the initiating language. This is referred to as type mapping.</li><li>The serialization and de-serialization needs to match in order to get the correct data on the receiving side.</li></ul><p>For <em><strong>e</strong></em> structs, the default is that physical fields (marked with <strong>%</strong>) are packed/unpacked.</p><p>For SystemVerilog items, the default is serialization of the fields that were added with the <strong>uvm_field_</strong>* macro. </p><p>For passing items between components, you should:</p><ul><li>Implement the data items:<ul><li>Make sure both ports, in both languages, handle same data items. <ul><li>If the items differ:<ul><li>Implement a new type, in either language.</li><li>You might have to implement a converter, converting from the original data item handled by the UVC, to the new data item</li></ul></li></ul></li></ul></li><li>Instantiate and connect the required ports<span> </span></li></ul>

NOTE: missing <p> tag at starting of content.

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Reporter

MayankA

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